Title A single - VDD half - clock - tolerant fine - grained dynamicvoltage scaling pipeline
In this paper, we propose a dynamic voltage scaling (DVS) policy for a fully asynchronous NoC suitable for low-power yet high-performance architectures. The DVS policy is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision. It judiciously adjusts switch voltage among only three voltage modes. The introduced architecture is simulated in 90nm CMOS technology with accurate Spice simulations. Experimental results show that the FIFO-adaptive DVS not only lowers the implementation cost, but also achieves another 31% energy-delay saving compared to the DVS policy based on link utilization, in a 90% saturated network.