Dynamic voltage and frequency management for a low-power embedded microprocessor

  title={Dynamic voltage and frequency management for a low-power embedded microprocessor},
  author={Takahiro Seki and Satoshi Akui and Katsunori Seno and Masakatsu Nakai and Tetsumasa Meguro and Tetsuo Kondo and Akihiko Hashiguchi and Hirokazu Kawahara and Kazuo Kumano and Masayuki Shimura},
  journal={IEEE Journal of Solid-State Circuits},
High-performance and low-power microprocessors are key to PDA applications. A dynamic voltage and frequency management (DVFM) scheme with leakage power compensation effect is introduced in a microprocessor with 128-bit wideband 64-Mb embedded DRAM. The DVFM scheme autonomously controls clock frequency from 8 to 123 MHz in steps of 0.5 MHz and also adaptively controls supply voltage from 0.9 to 1.6 V in steps of 5 mV, achieving 82% power reduction in personal information management scheduler… CONTINUE READING
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A 300MIPS/W RISC Core Processor with Variable Supply-Voltage Scheme in Variable Threshold-Voltage CMOS

  • K. Suzuki
  • Proc. CICC, pp. 587-590, May 1997.
  • 1997
1 Excerpt

A Voltage Reduction Technique for Digital Systems

  • P. Macken
  • ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 1990.
  • 1990
1 Excerpt

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