Dynamic termination output driver for a 600 MHz microprocessor

@article{Vishwanthaiah2000DynamicTO,
  title={Dynamic termination output driver for a 600 MHz microprocessor},
  author={S. Vishwanthaiah and Marcelo Ang and J N Starr and A. Taylor},
  journal={2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)},
  year={2000},
  pages={248-249}
}
Globally synchronous, multi-drop, bidirectional microprocessor system interfaces have the advantages of low latency and no synchronization penalty, and typically run at 100-120 MHz. Maximum operating frequency is limited by the time required for a signal transition initiated at the driving end to settle and reliably get sampled at the receiving end. Typical source-terminated systems (such as HSTL) require a round-trip transmission-line propagation delay to terminate the signal. With parallel… CONTINUE READING
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