Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures


Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreover, dynamically reconfigurable logic (DRL) architectures are an exciting alternative for embedded systems design. However, all previous approaches to DRL multi-context scheduling… (More)
DOI: 10.1145/774789.774831


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