Dynamic clock-frequencies for FPGAs


Most FPGA designs run at a fixed clock-frequency determined through static analysis in FPGA vendor supplied tools. Such a clocking strategy cannot take advantage of the full run-time potential of an application running on a specific device and in a specific operating environment. This paper describes methods for using dynamic clock-frequencies to overcome this limitation. We begin by describing a methodology for designing systems which allow dynamic clock-frequencies in FPGAs. We then present a framework for exploring the dynamic behaviour of suitable clock-frequencies for a number of FPGA applications in varied operational environments. Finally we introduce our AutoTEA system, which automatically adds circuitry to arbitrary FPGA designs for dynamically adjusting clock-frequency to a safe limit given current operating conditions. Our results show that dynamically clocking designs can lead to a speed improvement of 33–86% compared to using a fixed, statically estimated clock. 2006 Elsevier B.V. All rights reserved.

DOI: 10.1016/j.micpro.2006.02.006

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@article{Bower2006DynamicCF, title={Dynamic clock-frequencies for FPGAs}, author={Jacob A. Bower and Wayne Luk and Oskar Mencer and Michael J. Flynn and Martin Morf}, journal={Microprocessors and Microsystems}, year={2006}, volume={30}, pages={388-397} }