Dynamic Register Renaming Through Virtual-Physical Registers

@article{Arnal2000DynamicRR,
  title={Dynamic Register Renaming Through Virtual-Physical Registers},
  author={Teresa Monreal Arnal and Antonio Gonz{\'a}lez and Mateo Valero and Jos{\'e} Gonz{\'a}lez and V{\'i}ctor Vi{\~n}als},
  journal={J. Instruction-Level Parallelism},
  year={2000},
  volume={2}
}
Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel dynamic register renaming scheme that delays the allocation of physical registers until a late stage in the pipeline. We show that it can provide important savings in number of physical registers so it can significantly shorter the register file access time… CONTINUE READING

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