Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC

@inproceedings{Jarollahi2010DynamicPR,
  title={Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC},
  author={Hooman Jarollahi and Richard F. Hobson},
  booktitle={CDES},
  year={2010}
}
This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM counterparts. This design can be used as cache memory in processors and lowpower portable devices. The proposed SRAM cell… CONTINUE READING