Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures

Abstract

This paper discusses the incorporation of dynamic memory management during High-Level-Synthesis (HLS) for effective resource utilization in many-accelerator architectures targeting to FPGA devices. We show that in today’s FPGA devices, the main limiting factor of scaling the number of accelerators is the starvation of the available on-chip memory. For many… (More)
DOI: 10.1007/978-3-319-16214-0_10
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