Dynamic Memory Disambiguation Using the Memory Con ict Bu

  title={Dynamic Memory Disambiguation Using the Memory Con ict Bu},
  author={erDavid and Meng Y. Chen and W. ScottA.MahlkeJohnC.GyllenhaalWen-mei and HwuCenter},
To exploit instruction level parallelism, compilers for VLIW and superscalar processors often employ static code scheduling. However, the available code reordering may be severely restricted due to ambiguous dependences between memory instructions. This paper introduces a simple hardware mechanism, referred to as the memory con ict bu er, which facilitates static code scheduling in the presence of memory store/load dependences. Correct program execution is ensured by the memory con ict bu er… CONTINUE READING
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