Dynamic LDPC codes for nanoscale memory with varying fault arrival rates

@article{Ghosh2011DynamicLC,
  title={Dynamic LDPC codes for nanoscale memory with varying fault arrival rates},
  author={Shalini Ghosh and Patrick D. Lincoln},
  journal={2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)},
  year={2011},
  pages={1-4}
}
Modern state-of-the-art nanodevices exhibit remarkable electronic properties, but the current assembly techniques yield very high defect and fault rates. Static errors can be addressed at fabrication time by testing and reconfiguration, but soft errors are problematic since their arrival rates are expected to vary over the lifetime of a part. Usual designs consider error correcting codes that tolerate the maximum failure rate expected over the entire lifetime. In this paper, we propose using a… CONTINUE READING

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