Dynamic Compaction for High Quality Delay Test

@article{Wang2008DynamicCF,
  title={Dynamic Compaction for High Quality Delay Test},
  author={Zheng Wang and D. M. H. Walker},
  journal={26th IEEE VLSI Test Symposium (vts 2008)},
  year={2008},
  pages={243-248}
}
Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry… CONTINUE READING
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