Corpus ID: 27246501

DySER porting on Virtex-7

  title={DySER porting on Virtex-7},
  author={Ziliang Guo and M. Jalal and Zuyu Zhang},
The original implementation of integrating DySER with a OpenSPARC processor was done using the Virtex-5 FPGA platform. That effort faced a major limitation wherein the Virtex-5 platform did not have enough area to hold the entire OpenSPARC processor along with a full DySER block with its associated functional units (FU) and interconnects. As a result, benchmarks and studies had to rely on fixed configurations of DySER FUs instead of the dynamically routeable configuration that a full block… CONTINUE READING

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