Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications

  title={Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications},
  author={Brian P. Ginsburg and Anantha Chandrakasan},
  journal={Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.},
A dual 500MS/s, 5b ADC chip is implemented in a 0.18 mum CMOS process. The two ADCs have synchronized sampling for use in an I/Q UWB receiver. Each ADC has a 6-way time-interleaved successive approximation register topology and uses full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500MS/s operation with 7.8mW power consumption 
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