Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications

@article{Ginsburg2005DualS5,
  title={Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications},
  author={Brian P. Ginsburg and Anantha Chandrakasan},
  journal={Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.},
  year={2005},
  pages={403-406}
}
A dual 500MS/s, 5b ADC chip is implemented in a 0.18 mum CMOS process. The two ADCs have synchronized sampling for use in an I/Q UWB receiver. Each ADC has a 6-way time-interleaved successive approximation register topology and uses full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500MS/s operation with 7.8mW power consumption 
Highly Cited
This paper has 40 citations. REVIEW CITATIONS
24 Citations
7 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 24 extracted citations

References

Publications referenced by this paper.
Showing 1-7 of 7 references

Yamakido, “A CMOS 6b 500 MSample/s ADC for a hard disk drive read channel,

  • K. Y. Tamba
  • ISSCC Dig. of Tech. Papers,
  • 1999
1 Excerpt

Similar Papers

Loading similar papers…