Dual-rail asynchronous logic multi-level implementation

  title={Dual-rail asynchronous logic multi-level implementation},
  author={Igor Lemberski and Petr Fiser},
A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail synchronous Boolean network of complex (AND-OR) nodes. Next, the transformation into a dual-rail Boolean network is done. Each node is minimized under the formulated constraint to ensure hazard-free implementation. Then the technology dependent mapping procedure is… CONTINUE READING
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