Dual-VCC 8T-bitcell SRAM array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range

@article{Kulkarni2013DualVCC8S,
  title={Dual-VCC 8T-bitcell SRAM array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range},
  author={Jaydeep P. Kulkarni and Muhammad M. Khellah and Jim Tschanz and Bibiche M. Geuskens and Rinkle Jain and Stephen T. Kim and Vivek De},
  journal={2013 Symposium on VLSI Circuits},
  year={2013},
  pages={C126-C127}
}
A 14KB 8T-bitcell SRAM array is demonstrated in 22nm tri-gate CMOS with fine-grain dual-V<sub>CC</sub> assist techniques. V<sub>MIN</sub> limiting 8T-bitcell nodes are boosted selectively during read and write to improve overall chip-V<sub>MIN</sub>. Measurements show 130-270mV lower V<sub>MIN</sub> with 27-46% lower power at 0.4-1.6GHz for varying amounts of boosting, array activity and voltage regulator efficiency. 

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