Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing

@article{Shen2014DualSpeedTO,
  title={Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing},
  author={Kele Shen and Dong Xiang and Zhou Jiang},
  journal={2014 IEEE 23rd Asian Test Symposium},
  year={2014},
  pages={7-12}
}
The rapid growth in CMOS technology enables the technology of three-dimensional (3D) SoCs to be a promising approach for extending Moore's Law. Although the benefits supplied by 3D integration, managing test architecture design and reducing test cost are crucial challenges. Some powerful automatic test equipments (ATEs) that support different speed rate channels come into people's vision. In this paper, we propose a dual-speed TAM architecture optimization for 3D SoCs with hard dies, including… CONTINUE READING