Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA

@article{Won2016DualPhaseTT,
  title={Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA},
  author={Jun Yeon Won and Sun Il Kwon and Hyun Suk Yoon and Guen Bae Ko and Jeong-Whan Son and Jae Sung Lee},
  journal={IEEE Transactions on Biomedical Circuits and Systems},
  year={2016},
  volume={10},
  pages={231-242}
}
This paper describes two novel time-to-digital converter (TDC) architectures. The first is a dual-phase tapped-delay-line (TDL) TDC architecture that allows us to minimize the clock skew problem that causes the highly nonlinear characteristics of the TDC. The second is a pipelined on-the-fly calibration architecture that continuously compensates the nonlinearity and calibrates the fine times using the most up-to-date bin widths without additional dead time. The two architectures were combined… CONTINUE READING
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