Dual-Layer Adaptive Error Control for Network-on-Chip Links

@article{Yu2012DualLayerAE,
  title={Dual-Layer Adaptive Error Control for Network-on-Chip Links},
  author={Qiaoyan Yu and Paul Ampadu},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2012},
  volume={20},
  pages={1304-1317}
}
In this work, we present a new error control method to improve the energy efficiency and reliability of network-on-chip (NoC) links. The proposed method combines the error control coding (ECC) capabilities of the NoC's datalink and network layers to dynamically adjust the error control strength in variable noise conditions. Network-layer ECC is used in low noise conditions and error control strength is enhanced by adding datalink-layer ECC in high noise regions. To switch between the two ECC… CONTINUE READING

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Key Quantitative Results

  • Compared to previous solutions, the proposed method reduces residual packet error rate by up to four orders of magnitude, achieves up to 72% energy reduction and improves average latency by up to 64%.
  • Our method introduces more redundant check bits to each packet and uses the type-II hybrid ARQ, reducing the average energy per useful packet by up to 55%, 72%, 49%, and 21% compared to end-to-end SECDED, end-to-end CRC, end BCH and hop SECDED, and hop-to-hop adaptive ECC, respectively, as shown in Fig.
  • In low noise conditions , our method reduces the average energy by 7% compared to previous hop-to-hop ECC approaches.
  • 15, our method reduces the average energy by up to 36% for the 4-flit packet case; as the packet size increases to 16 flits, our method achieves up to 20% energy reduction.
  • Using the dual-layer ECC adaptation, our method reduces the total energy by up to 45% and 25%, compared to end BCH & hop SECDED and hop-to-hop adaptive ECC, respectively.
  • The proposed method achieves similar latency performance compared to other approaches in the low noise region, but reduces the latency by up to 64% and 43% compared to the end-to-end CRC and end-to-end SECDED, respectively, in high noise region.
  • Compared to other single-layer ECC approaches, the proposed method reduces average energy and latency by up to 72% and 64%, respectively.

Citations

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H2A: A hardened asynchronous network on chip

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Investigating Reliability and Security of Integrated Circuits and Systems

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A Fault Tolerance NoC Topology and Adaptive Routing Algorithm

  • 2016 13th International Conference on Embedded Software and Systems (ICESS)
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Optimizing the location of ECC protection in Network-on-Chip

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Research on congestion perception and control of network on chip

  • 2016 9th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI)
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A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance

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