Corpus ID: 17762647

Dual Edge Triggered Phase Detector for DLL and PLL Applications

@inproceedings{Kumar2015DualET,
  title={Dual Edge Triggered Phase Detector for DLL and PLL Applications},
  author={Prasanna Kumar and S. Ashok and Arun Kumar},
  year={2015}
}
An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional designs and can be operated at a frequency range of 250MHz to 1GHz.The proposed DET-PD is designed using… Expand

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References

SHOWING 1-10 OF 13 REFERENCES
A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator
TLDR
A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems that solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. Expand
A dual edge-triggered phase-frequency detector architecture [frequency synthesizer applications]
  • Syed Irfan Ahmed, R. Mason
  • Engineering, Computer Science
  • Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
  • 2003
TLDR
A dual-edge triggered PFD architecture that is independent of the duty cycle of the PFD inputs is proposed and the pull-in performance of a synthesizer using the new PFD is enhanced while the stability remains unchanged. Expand
PLL-based BiCMOS on-chip clock generator for very high speed microprocessor
A phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is employed to generate an internal clock synchronized to a reference clock from outside a chip, has been developed usingExpand
A register-controlled symmetrical DLL for double-data-rate DRAM
TLDR
This paper describes a register-controlled symmetrical delay-locked loop (RSDLL) for use in a high-frequency double-data-rate DRAM that is insensitive to variations in temperature, power-supply voltage, and process after being fabricated in 0.21 /spl mu/m CMOS technology. Expand
A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz
A fully integrated, phase-locked loop (PLL) clock generator/phase aligner for the POWER3 microprocessor has been designed using a 2.5-V, 0.40-/spl mu/m digital CMOS6S process. The PLL design supportsExpand
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto aExpand
A new true-single-phase-clocked double-edge-triggered flip-flop for low-power VLSI designs
  • Jinn-Shyan Wang
  • Engineering
  • Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97
  • 1997
A new CMOS double-edge-triggered flip-flop (DETFF) utilizing true single phase clocking is proposed as a promising storage element in low-power VLSI designs. Compared to the previously reportedExpand
A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications
A monolithic CMOS local oscillator utilizing a delay-locked loop (DLL)-based frequency multiplier technique to synthesize a 900-MHz carrier frequency with a low close-in phase noise is described. TheExpand
A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation
This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million-transistors microprocessor in a 0.35-??mExpand
CMOS Circuit Design, Layout, and Simulation
TLDR
Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples. Expand
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