Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

@article{Rostami2011DualV_thIF,
  title={Dual-\$V_\{th\}\$ Independent-Gate FinFETs for Low Power Logic Circuits},
  author={M. Rostami and K. Mohanram},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2011},
  volume={30},
  pages={337-349}
}
  • M. Rostami, K. Mohanram
  • Published 2011
  • Physics, Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thick ness optimization required to realize dual-Vth independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-Vth FinFETs with independent gates enable series and parallel merge… CONTINUE READING
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