Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction

Abstract

On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. In our previous work we have shown how the drowsy circuit---a… (More)
DOI: 10.1145/774861.774885

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