Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor

@article{Vezyrtzis2018DroopMU,
  title={Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor},
  author={Christos Vezyrtzis and Thomas Strach and Pierce I-Jen Chuang and Preetham Lobo and Richard F. Rizzolo and Tobias Webel and Pawel Owczarczyk and Alper Buyuktosunoglu and Ramon Bertran Monfort and David T. Hui and Susan M. Eickhoff and Michael S. Floyd and Gerard Salem and Sean M. Carey and Stelios G. Tsapepas and Phillip J. Restle},
  journal={2018 IEEE International Solid - State Circuits Conference - (ISSCC)},
  year={2018},
  pages={300-302}
}
Enterprise server processor designs, which operate at extreme high frequencies and power envelopes, depend critically on power supply noise mitigation techniques. With supply voltage scaling, very high current draws, and broad usage of clock gating, advanced solutions are needed for next-generation products to minimize droop mitigation response time, which can be defined as the latency from when a dangerous droop begins until a countermeasure is effective. 

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Key Quantitative Results

  • These noise mitigation features collectively yield a 4% improvement in z14TM product frequency with no loss in reliability margins, doubling the benefit seen in the previous generation from centralized threshold-based throttling alone.

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