Double-sampling architectures

@article{Nicolaidis2014DoublesamplingA,
  title={Double-sampling architectures},
  author={Michael Nicolaidis},
  journal={2014 IEEE International Reliability Physics Symposium},
  year={2014},
  pages={3D.1.1-3D.1.7}
}
Aggressive technology scaling impacts dramatically parametric yield and reliability in advanced nanometric nodes, and can become showstoppers when moving deeper to the sub-10nm domain. To mitigate this issue various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of these approaches have certain fundamental drawbacks such as: large performance penalty, and/or large area and power penalty, and/or false positives and false negatives… CONTINUE READING

From This Paper

Figures, tables, and topics from this paper.

Citations

Publications citing this paper.
Showing 1-5 of 5 extracted citations

Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic

2015 Euromicro Conference on Digital System Design • 2015
View 3 Excerpts
Highly Influenced

A Long Duration Transient Resilient Pipeline Scheme

IEEE Transactions on Device and Materials Reliability • 2017
View 2 Excerpts

Integrated Soft Error Resilience and Self-Test

2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) • 2016
View 1 Excerpt

Tackling long duration transients in sequential logic

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) • 2016
View 1 Excerpt

References

Publications referenced by this paper.
Showing 1-10 of 16 references

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

IEEE Journal of Solid-State Circuits • 2009
View 5 Excerpts
Highly Influenced

Circuit Logique protégé contre des perturbations transitoires", French patent, filed March 9, 1999 – US patent version "Logic Circuit Protected Against Transient Disturbances

M. Nicolaidis
2000
View 10 Excerpts
Highly Influenced

Time Redundancy Based Soft-Error Tolerant Circuits to Rescue Very Deep Submicron

M. Nicolaidis
IEEE VLSI Test Symposium", • 1999
View 10 Excerpts
Highly Influenced

RAZOR : circuit-level correction of timing errors for low-power operation

Shohaib Aboobacker
2011
View 13 Excerpts
Highly Influenced

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers • 2007
View 1 Excerpt

Similar Papers

Loading similar papers…