Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process

  title={Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process},
  author={C. Y. Wong and J. Sun and Y. Taur and C. S. Oh and R. Angelucci and B. Davari},
  journal={Technical Digest., International Electron Devices Meeting},
  • C. Y. Wong, J. Sun, +3 authors B. Davari
  • Published 1988
  • Materials Science
  • Technical Digest., International Electron Devices Meeting
  • The feasibility of fabricating dual-gate CMOS devices using the same implant to dope the polysilicon gates and to form shallow n/sup +/ and p/sup +/ source-drain junctions are demonstrated. With proper choices of polysilicon thickness, implant dose, and anneal conditions, flatband voltages approaching the degenerately doped values can be obtained simultaneously with the formation of shallow (less than 0.15 mu m) source-drain junctions. The process has been implemented in a high-performance 0.25… CONTINUE READING
    32 Citations
    Improving gate oxide integrity in p/sup +/pMOSFET by using large grain size polysilicon gate
    • 9
    Design of submicron PMOSFETs for DRAM array applications
    • 9


    Submicrometer-channel CMOS for low-temperature operation
    • 122
    Rapid Thermal Processing of Arsenic-Implanted Polysilicon on Very Thin Oxide
    • 3