Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process

  title={Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process},
  author={C. Y. Wong and Jack Y.-C. Sun and Yuan Taur and C. S. Oh and Renato Angelucci and Bijan Davari},
  journal={Technical Digest., International Electron Devices Meeting},
  • C. Wong, J. Sun, B. Davari
  • Published 11 December 1988
  • Engineering
  • Technical Digest., International Electron Devices Meeting
The feasibility of fabricating dual-gate CMOS devices using the same implant to dope the polysilicon gates and to form shallow n/sup +/ and p/sup +/ source-drain junctions are demonstrated. With proper choices of polysilicon thickness, implant dose, and anneal conditions, flatband voltages approaching the degenerately doped values can be obtained simultaneously with the formation of shallow (less than 0.15 mu m) source-drain junctions. The process has been implemented in a high-performance 0.25… 
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