Division Algorithm Design Using Field Programmable Gate Array

Abstract

This project is to design eight bit division algorithm program by using Xilinx ISE 10.1 software for simulation algorithm circuit partitioning through hardware Field Programmable Gate Array (FPGA). The algorithms are divide 8-bit dividend by 8-bit divisor for input and get the result 16-bit for the output. Circuit partitioning algorithms eight bits used to implement the distribution process for each program using the arithmetic and logic unit operations, called (ALU). All these operations using Verilog language in a program to be displayed on (LED) using the FPGA board. FPGA is a semiconductor device containing programmable logic components called "logic blocks", and programmable. Logic block can be programmed to perform the functions of basic logic gates such as AND, and XOR, or more complex combination of functions such as decoders or simple mathematical functions such as addition, subtraction, multiplication, and division (+, -, x, ÷). Finally, this project outlines the design and implementation of a new hardware divisor for performing 8-bit division. The error probability function of this division algorithm is fully characterized and contrasted against existing hardware division algorithms.

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Cite this paper

@inproceedings{Jaafar2014DivisionAD, title={Division Algorithm Design Using Field Programmable Gate Array}, author={A. Jaafar and M. M. Lazim and N . M . Z . Hashim and Azahari Salleh}, year={2014} }