Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors

@article{Raghavan2006DistributedLC,
  title={Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors},
  author={Praveen Raghavan and Andy Lambrechts and Murali Jayapala and Francky Catthoor and Diederik Verkest},
  journal={Proceedings of the Design Automation & Test in Europe Conference},
  year={2006},
  volume={1},
  pages={1-6}
}
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has been proven to be one of the most power hungry parts of the system. This paper introduces an architectural enhancement for the instruction memory to reduce energy and improve performance. The proposed distributed instruction memory organization requires minimal hardware overhead and allows execution of multiple loops in… CONTINUE READING
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Energy impact in the design space exploration of loop buffer schemes in embedded systems

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) • 2013
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IMOSIM: Exploration tool for Instruction Memory Organisations based on accurate cycle-level energy modelling

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) • 2012
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AIFSP: An Adaptive Instruction Flow Stream Processor

2011 IEEE Computer Society Annual Symposium on VLSI • 2011
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[2010] Energy Efficiency Using Loop Buffer based Instruction Memory Organizations

2010 International Workshop on Innovative Architecture for Future Generation High Performance • 2010
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