Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction

@article{Dutt2011DiscretizedNF,
  title={Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction},
  author={S. Dutt and H. Ren},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2011},
  volume={19},
  pages={1277-1290}
}
  • S. Dutt, H. Ren
  • Published 2011
  • Engineering, Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits without appreciable increase in wire length (WL). FlowPlace includes: 1) a timing-driven (TD) analytical global placer TAN that uses accurate pre-route delay functions and minimizes a combination of linear and quadratic objective functions; 2) a discretized network-flow-based detailed placer DFP that has new and effective techniques for… Expand
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A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement
  • H. Ren, S. Dutt
  • Mathematics, Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2011
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An effective white-space constraint satisfaction technique embedded in a network flow based detailed placer for standard cell designs that is suitable for both incremental as well as full detailed placement and has a provable high-probability of obtaining a legal placement even under tight white space (WS) constraints. Expand
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