Digitally assisted data converter design

@article{Murmann2013DigitallyAD,
  title={Digitally assisted data converter design},
  author={Boris Murmann},
  journal={2013 Proceedings of the ESSCIRC (ESSCIRC)},
  year={2013},
  pages={24-31}
}
Modern CMOS technologies provide digital signal processing capabilities at high integration density and low energy per operation. Hence, expending digital resources to enhance performance-limiting analog building blocks has become a widely explored paradigm in modern ICs. This paper reviews the state-of-the-art in digitally assisted data converter design and provides an overview of commonly used techniques. 

Citations

Publications citing this paper.
SHOWING 1-10 OF 18 CITATIONS

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  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2017
VIEW 6 EXCERPTS
CITES METHODS & BACKGROUND
HIGHLY INFLUENCED

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  • ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)
  • 2018
VIEW 1 EXCERPT
CITES METHODS

A/D converter fundamentals and trends

  • 2017 IEEE Custom Integrated Circuits Conference (CICC)
  • 2017

Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC

  • 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
  • 2017
VIEW 1 EXCERPT
CITES BACKGROUND

References

Publications referenced by this paper.
SHOWING 1-10 OF 107 REFERENCES

A Method to Increase the Accuracy of Fast-Serial-Parallel Analog-to-Digital Converters

  • IEEE Trans. Electronic Computers
  • 1964
VIEW 4 EXCERPTS
HIGHLY INFLUENTIAL

A 10.3GS/s 6b flash ADC for 10G Ethernet applications

  • 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
  • 2013
VIEW 2 EXCERPTS

A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

  • 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
  • 2013
VIEW 2 EXCERPTS

A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS

  • 2013 Symposium on VLSI Circuits
  • 2013
VIEW 2 EXCERPTS

ADC Performance Survey 1997-2013.

B. Murmann
  • [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
  • 2013

Information-Theoretic Approach to A/D Conversion

  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2013
VIEW 1 EXCERPT

Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS

  • 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
  • 2013
VIEW 2 EXCERPTS

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