Digital background calibration of a 10 b 40 M sample/s parallel pipelined ADC

@article{Fu1998DigitalBC,
  title={Digital background calibration of a 10 b 40 M sample/s parallel pipelined ADC},
  author={Dengwei Fu and Kirsti A. Dyer and S. Lewis and P W Hurst},
  journal={1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)},
  year={1998},
  pages={140-141}
}
This time-interleaved pipelined ADC uses monolithic digital background calibration to overcome the effects of the offset and gain mismatches between channels. The contributions here are use of digital background calibration to overcome these mismatches and implementation of these techniques in conjunction with the ADCs on one CMOS IC. Background calibration is done by adding a calibration signal to the ADC input and processing both simultaneously. A potential advantage of this approach is that… CONTINUE READING
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