Digital background calibration for memory effects in pipelined analog-to-digital converters

@article{Keane2006DigitalBC,
  title={Digital background calibration for memory effects in pipelined analog-to-digital converters},
  author={John P. Keane and Paul J. Hurst and Stephen H. Lewis},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2006},
  volume={53},
  pages={511-525}
}
Memory errors can occur in the stages of a pipelined analog-to-digital converter (ADC) due to several effects. These include capacitor dielectric absorption/relaxation, incomplete stage reset at high clock rates, and parasitic capacitance effects when opamps are shared between subsequent pipeline stages. This paper describes these sources of memory errors and the effect they have on overall ADC linearity. It is shown how these errors relate to and differ from interstage gain errors. Two new… CONTINUE READING
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