Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization

@article{Ragab2015DigitalBC,
  title={Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization},
  author={Kareem Ragab and Long Chen and Arindam Sanyal and Nan Sun},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2015},
  volume={62},
  pages={456-460}
}
This brief presents a digital background calibration technique that embraces comparator decision time to calibrate interstage gain errors and capacitor mismatches in pipelined analog-to-digital converters (ADCs). It does not modify the original analog signal path except for the addition of a comparator decision time binary quantizer built by simple digital gates. The technique does not limit either the ADC input signal swing or bandwidth. Simulation results for a 12-bit pipelined ADC show that… CONTINUE READING

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