Corpus ID: 18331207

Differential static ultra low-voltage CMOS flip-flop for high speed applications

@inproceedings{Berg2011DifferentialSU,
  title={Differential static ultra low-voltage CMOS flip-flop for high speed applications},
  author={Yngvar Berg},
  year={2011}
}
  • Y. Berg
  • Published 29 December 2011
  • Materials Science
In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digital low-voltage CMOS application. 

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