Differential Time Signaling Data-Link Architecture

@article{Rashdan2013DifferentialTS,
  title={Differential Time Signaling Data-Link Architecture},
  author={Mostafa Rashdan and Abdel Yousif and James W. Haslett and Brent Maundy},
  journal={Journal of Signal Processing Systems},
  year={2013},
  volume={70},
  pages={21-37}
}
A new time-based high-speed data-link architecture, which we call Differential time Signaling (DTS) is presented. A clock pulse is embedded in the transmitted signal and is used as a time reference against which the rising and falling data pulse edge timings are compared. Using the DTS approach, data encoding is achieved by spacing the time between the embedded clock edges and the data pulse edges using a hierarchical time-delay resolution assignment to each bit in the data sequence. The… CONTINUE READING
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Citations

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  • 2013
VIEW 4 EXCERPTS
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  • 2012
VIEW 9 EXCERPTS
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  • 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
  • 2018
VIEW 4 EXCERPTS
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  • 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)
  • 2016
VIEW 1 EXCERPT
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  • 2016 28th International Conference on Microelectronics (ICM)
  • 2016
VIEW 1 EXCERPT
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  • 2014 IEEE 44th International Symposium on Multiple-Valued Logic
  • 2014
VIEW 1 EXCERPT
CITES METHODS

References

Publications referenced by this paper.
SHOWING 1-10 OF 26 REFERENCES

A new time-based architecture for serial communication links

  • 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)
  • 2009
VIEW 14 EXCERPTS
HIGHLY INFLUENTIAL

A low power and high speed PPM design for ultra wideband communications

  • 2008 Canadian Conference on Electrical and Computer Engineering
  • 2008
VIEW 3 EXCERPTS
HIGHLY INFLUENTIAL

A 1.62/2.7-Gb/s adaptive transmitter with two-tap preemphasis using a propagation-time detector

Kao, S.-Y, Liu, S.-I
  • IEEE Transaction on Circuits and Systems II, Express Briefs (USA),
  • 2010

A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS

  • 2010 IEEE International Solid-State Circuits Conference - (ISSCC)
  • 2010
VIEW 1 EXCERPT

A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology

Kao, S.-Y, Liu, S.-I
  • IEEE Transaction on Circuits and Systems II, Express Briefs (USA),
  • 2010

A 20Gb/s 40mW equalizer in 90nm CMOS technology

  • 2010 IEEE International Solid-State Circuits Conference - (ISSCC)
  • 2010
VIEW 1 EXCERPT

A 5Gbs transceiver with an ADCbased feedforward CDR and CMA adaptive equalizer in 65 nm CMOS (pp. 168–169)

H Yamaguchi
  • San Francisco: Proc. ISSCC Dig. Tech. Papers
  • 2010

Data link design using a time-based approach

  • Proceedings of 2010 IEEE International Symposium on Circuits and Systems
  • 2010
VIEW 2 EXCERPTS

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