Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

@article{Wong1998DeviceDC,
  title={Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation},
  author={H.-S. Philip Wong and D. J. Frank and P. M. Solomon},
  journal={International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)},
  year={1998},
  pages={407-410}
}
We present a simulation-based analysis of device design at the 25 nm channel length generation. Double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's are considered. Dependencies of short-channel effects on channel thickness and ground-plane bias are illustrated. Two-dimensional field effects in the gate insulator (high k) and the buried insulator (low k) in single-gate SOI are studied. 
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