Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

@article{Zhan2011DevelopmentOF,
  title={Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization},
  author={Chau-Jie Zhan and J. R. Juang and Yu-Min Lin and Yu-Wei Huang and K. S. Kao and Tsung-Fu Yang and Su-Tsai Lu and John H. Lau and Tai-Hong Chen and Robert Lo and Ming-Jer Kao},
  journal={2011 IEEE 61st Electronic Components and Technology Conference (ECTC)},
  year={2011},
  pages={14-21}
}
3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on… CONTINUE READING