Detection conditions for errors in self-adaptive better-than-worst-case designs

Abstract

The rapidly increasing variability in circuit performance in highly scaled technologies has given rise to novel “better-than-worst-case” circuit design methods. They aim to overcome worst-case clock timing requirements by employing a shorter clock period and allowing occasional errors to occur; these are detected and recovered from by low-cost… (More)
DOI: 10.1109/ETS.2014.6847794

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Cite this paper

@article{Polian2014DetectionCF, title={Detection conditions for errors in self-adaptive better-than-worst-case designs}, author={Ilia Polian and Jie Jiang and Adit D. Singh}, journal={2014 19th IEEE European Test Symposium (ETS)}, year={2014}, pages={1-6} }