Designing and simulation of full adder cell using FINFET technique

@article{Saraswat2013DesigningAS,
  title={Designing and simulation of full adder cell using FINFET technique},
  author={R. C. Saraswat and Sham Akashe and Sudhir Babu},
  journal={2013 7th International Conference on Intelligent Systems and Control (ISCO)},
  year={2013},
  pages={261-264}
}
This paper proposes a 1-Bit full adder cell using Double Gate FINFET (Fin Shaped Field Effect Transistor) at 45nm CMOS technology. The intention of this paper is to reduce leakage power and leakage current of 1-bit Full Adder while maintaining the competitive performance with few transistors are used (transistors count 10). A new high performance 1-bit Full… CONTINUE READING