Designing an asynchronous processor using Petri nets

@article{Semenov1997DesigningAA,
  title={Designing an asynchronous processor using Petri nets},
  author={Alexei L. Semenov and Albert Koelmans and Lee Lloyd and Alexandre Yakovlev},
  journal={IEEE Micro},
  year={1997},
  volume={17},
  pages={54-64}
}
Using a simple example, we demonstrate how to design and analyze asynchronous systems from labeled Petri net specifications, later refining, transforming, and translating them for implementations. 

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References

SHOWING 1-10 OF 28 REFERENCES
Modular, asynchronous control structures for a high performance processor
TLDR
The example shows that Petri nets, and asynchronous circuits assembled from the few module types introduced below, are suitable for expressing all control functions found in high performance computer systems.
Petri Net Analysis Using Boolean Manipulation
TLDR
Examples are presented that show how all the reachable states of a Petri net can be efficiently calculated and represented with a small BDD, and properties requiring an exhaustive analysis of the state space can be verified in polynomial time in the size of the BDD.
Petri nets: Properties, analysis and applications
TLDR
The author proceeds with introductory modeling examples, behavioral and structural properties, three methods of analysis, subclasses of Petri nets and their analysis, and one section is devoted to marked graphs, the concurrent system model most amenable to analysis.
Practical verification and synthesis of low latency asynchronous systems
TLDR
A software prototype CAD tool called Analyze was written as part of this dissertation to allow the principles of this work to be tested and applied and to verify when a specification obeys all the burst-mode rules and can be automatically synthesized into an implementation.
Symbolic Model Checking
TLDR
Using symbolic model checking techniques it is possible to verify industrial-size finite state systems and models with more than 10120 states have been verified using special techniques.
Synthesis of self-timed VLSI circuits from graph-theoretic specifications
TLDR
This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs), and develops a number of analytical results which establish the equivalence between the static structure of nets and their underlying firing sequence semantics.
The Design and Implementation of an Asynchronous Microprocessor
TLDR
This thesis introduces the Micropipeline approach and discusses the design, organization, implementation and performance of the asynchronous ARM microprocessor which was constructed in the course of the OMI-MAP project.
Stubborn sets for reduced state space generation
  • A. Valmari
  • Computer Science
    Applications and Theory of Petri Nets
  • 1989
TLDR
The “stubborn set” theory and method for generating reduced state spaces and a more advanced version suited to the analysis of properties of reactive systems is developed.
TITAC: design of a quasi-delay-insensitive microprocessor
TLDR
TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption for efficient signal generation and data transfer.
...
...