Designing a clock cycle accurate application with high-level synthesis

@article{Lahti2016DesigningAC,
  title={Designing a clock cycle accurate application with high-level synthesis},
  author={Sakari Lahti and Jarno Vanne and Timo D. H{\"a}m{\"a}l{\"a}inen},
  journal={IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society},
  year={2016},
  pages={4756-4761}
}
During the recent years, high-level synthesis (HLS) has gained traction as a viable alternative to traditional handwritten register transfer level code in describing digital systems. This has been attributed to the maturing of the HLS tools and improving quality of their results. However, most published applications are data path intensive as HLS offers good tools for loop optimization, such as pipelining and loop unrolling. HLS is seldom applied to control-oriented applications since clock is… CONTINUE READING

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Key Quantitative Results

  • Compared with a corresponding handwritten VHDL implementation, the HLS version consumes 84% more area at the same performance but productivity is increased by 100% at the first design time and even more with further design iterations.

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