Design techniques for high performance CMOS flash analog-to-digital converters

  title={Design techniques for high performance CMOS flash analog-to-digital converters},
  author={Sunghyun Park and M. P. Flynn},
  journal={Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.},
  pages={I/131-I/134 vol. 1}
This paper reviews the limitations in the performance of CMOS flash ADCs. Methods to enhance sampling rate, such as interleaving and latch cascading, are discussed, and a method that employs inductors to improve comparator performance is presented. We also consider the benefits and trade-offs of implementing a flash ADC without a track-and-hold. 


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A 1.8-V 6bit 1.3-GHz flash ADC in 0.25 μm CMOS

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2 Excerpts

Analog-Digital Interfaces classnotes

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1 Excerpt

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