Design-specific variation in pattern transfer by via/contact etch process: full-chip analysis

@article{Sukharev2009DesignspecificVI,
  title={Design-specific variation in pattern transfer by via/contact etch process: full-chip analysis},
  author={Valeriy Sukharev and Ara Markosian and Armen Kteyan and Levon Manukyan and Nikolay Khachatryan and Jun-Ho Choy and Hasmik Lazaryan and Henrik Hovsepyan and Seiji Onoue and Takuo Kikuchi and Tetsuya Kamigaki},
  journal={Journal of Micro-nanolithography Mems and Moems},
  year={2009},
  volume={8},
  pages={043007}
}
A novel model-based algorithm provides a capability to control full-chip design-specific variation in pattern transfer caused by via/contact etch (VCE) processes. This physics-based algorithm is capable of detecting and reporting etch hot spots based on the fabrication-defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design… 
3 Citations
Design specific variation in via/contact pattern transfer: Full chip analysis
TLDR
A novel model-based algorithm provides a capability to control full chip design specific variation in pattern transfer caused by via/contact etch processes and can be used as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design.
Challenges for patterning process models applied to large scale
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The new process simulation challenges that are emerging as the industry approaches sub-0.25 k1 patterning will be outlined, including 3D effect...
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To maximize performance and process utilization in microprocessor designs, a timing analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of designs is developed and validated, thereby reducing chip area and maximizing performance while ensuring chip functionality, improved process utilization and yield.

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