A design procedure is developed for the integration of RF-circuits in a 0.6 /spl mu/m CMOS process on latchup resistant epi-substrates. The proposed method was developed by performing resimulation of a fully integrated medium power amplifier (PA) which delivers 21 dBm output power and 31% power added efficiency (PAE) at 1.1 GHz. To understand the measured circuit behavior, a detailed description of all wires with respect to capacitive substrate coupling and inclusion of mutual inductances is necessary. Scalable lumped element models based on foundry given process parameters are developed which allow the inclusion of relevant layout parasitics. Yield analysis based on the foundry process parameter spreads show that the fabricated PA will have a minimum PAE of 21% at 100% yield.