FPGA Based Extension to the Multichannel Pixel Readout ASIC
- P. Maj
- Proceedings of IEEE NSS
This paper presents the design and simulation results of the ultrafast LVDS I/O interface designed in 40 nm CMOS process. The LVDS transmitters and receivers were designed to support a data transfer of a multichannel Integrated Circuit dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The transmitter is based on the current switching bridge architecture while the receiver is built of the inverting comparator with hysteresis. The LVDS I/O interface is supplied from 2.5 V and 0.9 V supply voltage. The transmitter and receiver occupy respectively 0.1 mm<sup>2</sup> and 0.009 mm<sup>2</sup> of chip area. The static/dynamic power consumption of the transmitter and receiver are respectively equal to 17.9/26.4 mW and 7.1/12.1 mW.