Design of the HP PA 7200 CPU

  title={Design of the HP PA 7200 CPU},
  author={Kenneth K. Chan and Cyrus C. Hay and John R. Keller and Gordon Kurpanek and Francis X. Schumacher and Jason Zheng},
The PA 7200 incorporates a number of enhancements specifically designed for a glueless four-way multiprocessor system with increased performance on both technical and commercial applications.10-11 On the chip is a multiprocessor system bus interface which connects directly to the Runway bus described in Article 2. The PA 7200 also has a new data cache organization, a prefetching mechanism, and two integer ALUs for general integer superscalar execution. The PA 7200 artwork was scaled down from… CONTINUE READING
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