Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit

@article{Park2004DesignOQ,
  title={Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit},
  author={Soo Jin Park and Byoung Hee Yoon and Kwang Sub Yoon and Heung Soo Kim},
  journal={Proceedings. 34th International Symposium on Multiple-Valued Logic},
  year={2004},
  pages={198-203}
}
A multi-valued logic (MVL) pass gate is an important element in configuring multi-valued logic. Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and the quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates. In addition, we designed quaternary truncated sum (QTS) and… CONTINUE READING
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