Corpus ID: 18145716

Design of process invariant Delay Lock Loop ( DLL ) ECE 6770-Final Report

  title={Design of process invariant Delay Lock Loop ( DLL ) ECE 6770-Final Report},
  author={M. Nagaraju},
Random device mismatch have a significant impact on the performance of analog circuits. This report discusses the design of a Delay Lock Loop (DLL) which is insensitive to process variation. The DLL is optimized for reduction in the variation of threshold voltage variations and is intended to be used in a clock and data recovery circuit with an input bit rate of 500 Mbps. The performance specifications of the DLL are also analyzed. The DLL is expected to be fabricated in the AMI 0.6 um… Expand


Device mismatch and tradeoffs in the design of analog circuits
  • P. Kinget
  • Engineering
  • IEEE Journal of Solid-State Circuits
  • 2005
Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves withExpand
A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications
A monolithic CMOS local oscillator utilizing a delay-locked loop (DLL)-based frequency multiplier technique to synthesize a 900-MHz carrier frequency with a low close-in phase noise is described. TheExpand
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
  • J. Tschanz, J. Kao, +4 authors V. De
  • Mathematics, Computer Science
  • 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
  • 2002
Measurements on a 150 nm CMOS test chip show that on-chip bidirectional adaptive body biasing compensates effectively for die-to-die parameter variation to meet both frequency and leakageExpand
Process-Invariant Current Source Design: Methodology and Examples
These are the first measured results showing effective circuit design techniques that reduce the impact of process variations by such magnitude, and can be an effective way to improve circuit yield as process variations increase. Expand
Where CMOS is going: trendy hype vs. real technology
  • Tze-Chiang Chen
  • Engineering, Computer Science
  • 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers
  • 2006
The infusion of new materials and device structures will extend the development lifetime of silicon CMOS by at least ten years and Cooperative circuit/technology co-design, and architectures developed concurrently with these new device innovations will provide a comprehensive solution to the challenges of deep submicron CMOS. Expand
Solid-State Circuits Conf. (ISSCC)
  • Dig. Tech. Papers
  • 2006
Solid-State Circuits Conference Digest of Technical Papers. 43rd ISSCC
  • IEEE International
  • 1996
Appendix: I) Verilog code for enabling the ring oscillators sequentially
  • Appendix: I) Verilog code for enabling the ring oscillators sequentially