Corpus ID: 18145716

Design of process invariant Delay Lock Loop ( DLL ) ECE 6770-Final Report

@inproceedings{Nagaraju2008DesignOP,
  title={Design of process invariant Delay Lock Loop ( DLL ) ECE 6770-Final Report},
  author={M. Nagaraju},
  year={2008}
}
Random device mismatch have a significant impact on the performance of analog circuits. This report discusses the design of a Delay Lock Loop (DLL) which is insensitive to process variation. The DLL is optimized for reduction in the variation of threshold voltage variations and is intended to be used in a clock and data recovery circuit with an input bit rate of 500 Mbps. The performance specifications of the DLL are also analyzed. The DLL is expected to be fabricated in the AMI 0.6 um… Expand

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Appendix: I) Verilog code for enabling the ring oscillators sequentially
  • Appendix: I) Verilog code for enabling the ring oscillators sequentially