Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events

Abstract

In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESDtransient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESDtransient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.

DOI: 10.1109/ISCAS.2011.5937835

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Cite this paper

@inproceedings{Yeh2011DesignOP, title={Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events}, author={Chih-Ting Yeh and Yung-Chih Liang and Ming-Dou Ker}, booktitle={ISCAS}, year={2011} }