Design of power efficient All Digital Phase Locked Loop (ADPLL)

Abstract

This paper presents a power efficient design of All Digital Phase Locked Loop (ADPLL). The proposed ADPLL uses power optimized digital loop filter instead of the conventional one. The power optimization of digital loop filter is carried out with the aid of clock gating technique without degrading the performance of the overall system. The proposed… (More)

3 Figures and Tables

Topics

  • Presentations referencing similar topics