Design of multigigabit multiplexer-loop-based decision feedback equalizers

  title={Design of multigigabit multiplexer-loop-based decision feedback equalizers},
  author={Keshab K. Parhi},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
This paper presents novel approaches for pipelining of parallel nested multiplexer loops and decision feedback equalizers (DFEs) based on look-ahead techniques. Look-ahead techniques can be applied to pipeline a nested multiplexer loop in many possible ways. It is shown that not all the look-ahead approaches necessarily result in improved performance. A novel look-ahead approach is identified, which can guarantee improvement in performance either in the form of pipelining or parallelism. The… CONTINUE READING
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Publications referenced by this paper.
Showing 1-5 of 5 references

Pipelining of parallel multiplexer loops and decision feedback equalizers

2004 IEEE International Conference on Acoustics, Speech, and Signal Processing • 2004
View 1 Excerpt

Low-energy CSMT carry generators and binary adders

IEEE Trans. VLSI Syst. • 1999
View 1 Excerpt

Pipelining in algorithms with quantizer loops

K. K. Parhi
IEEE Trans. Circuits Syst., vol. 37, no. 7, pp. 745–754, Jul. 1991. • 1991
View 2 Excerpts

Techniques for High-Speed Implementation of Nonlinear Cancellation

IEEE Journal on Selected Areas in Communications • 1991
View 2 Excerpts

Optimizing synchronous circuitry by retiming

C. Leiserson, F. Rose, J. Saxe
3rd Caltech VLSI Conf., 1983, pp. 87–116. • 1983
View 2 Excerpts

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