Design of modified low power booth multiplier

@article{Prabhu2012DesignOM,
  title={Design of modified low power booth multiplier},
  author={Anmiv S Prabhu and Vijay Elakya},
  journal={2012 International Conference on Computing, Communication and Applications},
  year={2012},
  pages={1-6}
}
The design of normal multiplier consumes most of the power in DSP processors. In order to reduce the power consumption of multiplier, the low power Booth recoding methodology is implemented by recoding technique. This booth decoder will increase number of zeros in multiplicand. Booth multiplier has booth decoder to recode the given input to booth equivalent. Hence the number of switching activity will be reduced so the power consumption of the design can be reduced. The input bit coefficient… CONTINUE READING
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